miiller



March 10, 1964 H. s. MULLER 3,124,677 COMPARATOR UTILIZING THRESHOLD ORGANS Filed July 18, 1960 3 Sheets-Sheet 1 (V f my punir/$4501- l f /I 50 :IJ F/LTEQ 52 \42 M/PUT.: ouv-pur PLO UQ \44 45 cpv/TY Il Fj- 2" INVENTOR. HENRY S. M//L-LEZ March 10, 1964 H. s. MULLER COMPARATOR UTILIZING THRESHOLD ORGANS 5 Sheets-Sheet 2 Flled July 18, 1960 INVENTOR.

Hau/2y 5. Ml/LLEZ BY 90K" l/ Irfan/iv March 10, 1964 H. s. MULLER 3,124,677

coupm'roa ummm maEsHoLn oRGANs Filed July 18, 1960 3 Sheets-Sheet 3 k 0 TUA/MEL s o/ooe 8 INVENTOIL HEA/QY 5- M/ILLYEQ "Y 5MM/7W.

ran/5% United States 3,124,671 Pfented Mar. 1go, 1964 3,124,677, COMPARATOR UTILIZING THRESHOLD ORGANS Henry S. Miiller, Trenton, N .J assigu'or to Radio Corporation of America, a corporation of Delaware Y Filed July 18, 1960, Ser. No. 43,660 15 Claims. (C1. 23S-177) This invention relates to' information handling devices and, more particularly, to a method and apparatus for comparing two binary quantities.

1Fundamental to d ata processing systems are apparatus which effect comparison between binary quantities or characters. In some applications, certain sorting and conditional transfer applications for example, it is: riequired that the comparatorA provide not only an indication of equality, but also an indicationas to which of the quantities is the larger, or smaller, when the compared quantities are unequal.

Most digital computers employ the binary systernof notation for representing information. In general, a predetermined number of binary digits are selectedas ay character length, and each desired letter, symbol, number, etc. may be represented by a different combination of binary ones and zeroes in a character. l

It is desirable in the interests of high speed that the binary digits of a character be handled' in parallel by the comparator. It is also desirable that the comparator include a minimum number of logic networks and stages, and that the networks and stages employed have a high operating speed in order to reduce the decision-'making time to'a minimum;

Accordingly, it is an object of this invention topprovide improved apparatus for comparing binary quantities.

It is another object of this invention to provide a comparator device for comparing rapidly binary information encoded as parallel digits.

It is still another object of this invention to' provide an improved digital comparator which provides an indication when the compared quantities are equal, and which provides an indication as to which quantity is the larger, or smaller, when the compared quantities are unequal.

It is yet another object of this invention to provide an improved digital comparator which has a reduced number of components and a high operating speed.

In accordnce with one embodiment of the invention, these and other objects are accomplished by first. and second threshold organs, means for applying to said rst and second organs signals weighted according to digit signincance and representing, respectively, the binary digits of first and second binary quantities. to be compared, means for applying to said iirst and second organsv signals Weighted according to digit significance and representing, respectively, the bit-by-bit binary complements of the digits of saidsecond and irst quantities, and means for sampling the outputs of said organs.

In the accompanying drawing, like reference'characters refer to like components, and:

FIGURE l is a generalized block diagram of a comparator according to the invention; v

FIGURE 2 is a diagram of a parametric phase locked oscillator and means for Weighting-the input signals thereto;

FIGURE 3 is a schematic diagram ofthe FIGURE l comparator implemented with phase locked oscillators;

FIGURE 4 is a timing diagram of the three phase pump energizing source of FIGURE 3;

FIGURE 5 is a'schematic diagram of` a tunnel diode threshold organ;` i

FIGURE 6 is a volt-ampere characteristic of the tunnel diode of FIGURE 5 FIGURE 7 isa schematic diagram of a baseband complementary device; and

the" mostl significant YThe Presence. ,of

FIGURE s is a bio'ci diagram of another comparator arrangement according to theinvention. Before proceeding with a description of the apparatus, a preliminary discussion of triev binary information signals occurring d'u'ri'n'gmth'e comparison process and their relation is given to, facilitate the readers understanding ofthe invention. Itis believed thatthedescription of the interconnectionwof the various units; of the comparator and its operation can then be explained in a more simple and understandablel manner in the light of the review.

Binary notation' has many variations evolving from a pure binarysystemj. In purev binarynotatiomit is customary to write a number (as in decimal notation) with digit at the leftmost position, and with the digits of lesser significance arranged in succeeding digit positions, and in orden; left to, right. At `each digit position, only oneof `'two' values is ed'v'ployed, binary fl 4or binary 0. A binary number A may be expressed generally as'follows:

(1') where an is the digit or bit of the n-l- 1th digit position, and where an, an 1, etc each may be either binary l or O.

The digit positions represent the successive powers to the base two, starting with the least, or zero, power at the' right, in contrast, with the successive powers tothe base lten employed in the decimal system of notation. a binary in a digit position .means that the Correspndingpower .0f two isadddinthe numbergth presence of abinary 0 means that the power Qfwaorresponding fo` thatpositon is. not added t, The

4or bits, has a Weight or. value in the decimal system corresponding" to its signiiicance in the number, as expressed by the numerical coeicient in Formula 2. Re-

yfer'ring to the above example, the weights of the binary ls in the binary number 1011 are 8, 2 and 1, respectively, reading irom left to right.

Other` binary coding scheme-s are known inthe art and need not be -discussedhere..A In general, in these binary systems, alphabetic chanacters are coded such that the binary values of the characters increase from A to Z, Ithat is, the vbinary value orf the. letter B` is greatery than that .ofjA .and less than that of C.. Therefore, two binary qillantities'representing letters of the alphabet may be compared by comparing the decimal equivalents of their binary representations. The present invention is vnot limited to usie'withl any particular system of binary notation'. However, the invention 'will be describemfor convenience, in connection with the pure binary notation scheme` of number representation.

A further quantity, deiined as fthe 'bit by bit ones complement, or binary complement, of the binary quantity A is as follows:

wliereo;has'tliemaning' not an. The decimal equiv- `alent n; of is then:

1f', frfexampie," A'=1011-, than 1:0100 and ZD=22(1) or 4.

Let X and Y be two binary numbers or quantities to be compared, where Y=ynyn1 yzyllo (6) The decimal equivalents XD, YD of these binary quantiand ties X and Y, and the decimal equivalents XD and YD of the bit ones complements X and Y are as follows:

v Assume that the binary quantity X is greater than Y. PDhen,

Inequality (12) may be mechanized by `a threshold organ in a manner to ybe described hereinafter. A threshold organ may be dened for present purposes as a multiinput device having a threshold, and providing a first output when the summation of the inputs thereto equals or exceeds the threshold, and a second, different output when .the summation of the inputs is less than the threshold. lIn some applications, depending upon the type off` D signals used to represent the binary digits, Ia special case exists where the threshold of the organ may be zero. In any case, the signals representing the various binary digits applied to the organ are effectively weighted in accordance with the particular significance of the digits. rIhe term threshold organ is used here in a generic sense and, as will be apparent from the :following discussion, may include certain types of devices sometimes referred to as majority organs or gates.

In terms of number representation, several conclusions may be dra-wn with respect to .the summation term in inequality (12). If the electrical signals employed to represent the binary digits are endowed with veto or cancellation power, then the value of the summation term equals a null. Such a 4condition exi-sts, :for example,

`Where phase script notation is employed, that is, where a binary l is .a radio Ifrequency (rf) signal of one phase and a 0 is an rf signal of the counter phase at the same frequency `and having the same amplitude. Signals representing 1 and 0 in phase script cancel or veto each other if they have equal magnitudes. The same condition obtains where -a 1 is -a pulse of one polarity and amplitude and a 0 is a pulse of the opposite polarity and the same amplitude. The right-hand Y or summation term of inequality (12) has a value equal to The technique employed in deriving inequality (12N) may be extended to derive equations expressing the conditions :whe-re X=Y and Y X.

" Inequality (16) may be mechanized gby a'second threshsired that the first organ provide said iirst output only when X Y, then the threshold should be set slightly higher than the value of the summation term of inequality (l2) or Equation 13. Likewise, the threshold of the second organ should be set slightly higher than the value of the summation term of Equation 14 or inequality (16) if the second organ is to provide said iirst output only when Y X. Equality of X and Y then may be recognized by the simultaneous occurrence of said second output from both organs. If, on the other hand, the thresholds are set such that the rst organ provides said rst output when X Y or X Y, and the second organ provides said first output when Y=X or Y X, equality of X and Y may be recognized by the simultaneous occurrence of said lirst output from both organs. The rst method of setting the threshold is preferred in most applications.

FIGURE 1 is a block diagram of a preferred embodiment of a comparator according to the invention. Common circuit connections such as circuit ground are omitted for clarity of drawing. Blocks 10 and 12 include multilinput threshold organs which have the characteristics dethe block 10, adjacent to the arrows on the input leads denote the weights of the input signals applied to the threshold organ 10. These weights correspond to the coefficients of the binary digits as given by Equation 7.

A second plurality of input signals corresponding to the bit by bit binary complements of the digits y0 yn of the quantity Y are applied to a second plurality of input terminals of the threshold organ 10. These inputs are designated y0 These inputs also are weighted at the threshold organ 10 in accordance With their digit significance. Applied to another terminal of the threshold organ 10 is a threshold (T) voltage or signal. The threshold Voltage or signal is selected in accordance with inequality (12) and the discussion which follows immediately thereafter. If X is greater than Y, then the summation of the information input signals to the threshold organ is greater than the value of the term Zwarts.)

k=0 This term, as described heretofore, .hasa value of ,either or zero. The threshold `(T) voltage orsignal isselected in the general case to have a magnitude ywhich is `slightly greater than VkO or zero, depending upon the particular signal representation of the binary digits.

Signals corresponding to the binary digits y0 yn are applied to a plurality of input terminals of the second threshold organ 12. Signals E; xn corresponding to the binary complements of the individual digits x0 xn areiapplied to another plurality of input terminals of the second organ 12. Also applied to this organ '12 is' a threshold(T)"signal Yor voltage having the same value as the threshold (T) of the first organ 1,0.

The rst threshold organ l10 provides a first output, which may represent binary IQvvhen the binary quantity X is greater than the quantity Y, and a second, different output, which may correspond to binary 0 when Xvis equal to or less than Y. The second threshold organ `12 provides the first ,output when Y is greater than X and ythe second output when Y`is equal to, or less than X.

The output of the first threshold organ 10 is applied to a first output terminal 14 over a line 16, and also is applied to a binary complementing device 18, designated C. The complementing `device 18 provides an output signal representing a binary l in respons/e to a received signal representing a binary 0, and vice versa. The output of the second threshold organ l12. is applied Yto a second output terminal'22 over aline '.24 andalso is applied to the input of a complementing device 26; The complementing :device 26 may be identicalto the ycomplementing device 18'.

The outputs of the complementing devices 18 and 26 are applied to first andsecond 'input terminals of a third threshold organ 30. yA threshold (Ta) signal or voltage is applied to a third input of the threshold organ 3h. The value of the threshold signal (T a) is `selected such that a first output corresponding to a binary l is provided by the organ St) only when the outputs of both of the complementing devices 18, 26 correspond to binary "l. The third organ 30 may be a simple and gate in many cases. The output of the third threshold organ 30 is applied to an output terminal 32 over a line 34. l

The output system fof the threshold organs described is arranged so that a signal corresponding to a binary l is present at only one output terminal 14, 22, 32 at any one time. Such a signal appearing at an output terminal has the significance indicated bythe notation beneath that output terminal inFIGURE 1. For example, a signal corresponding to binaryfl at output terminal 1d signifies that X is greater than Y.

It will be apparent that the complementing devices ,18, 26 may be eliminated if the thresholds of organs 10, 12 are adjusted so that both of theseV organsV provide an output representingbinary l when X Vand Y are equal.

One device suitable for use as a threshold organ 10, 12 in practicing the invention is a parametric phase-locked oscillator (PLO) of the type described in an article by Fred Sterzer in the Proceedings of the IRE, August y1959, atI page 1313. Such oscillators, as is known, are Vcapable of oscillating in the kilomegacycle range with high switching speed. A PLO may berused as the threshold organ in a system whereina binary l is represented by an RF signal of one phase, and a binary "0 is represented by an RF signal of a counter phase at the same frequency and amplitude. The input signals to such a device have veto or cancellation power. That is to say, a binary "1 signal cancels a binary 0 signal of the same weight.

Operation of a PLO is described in detail in the aforementioned article and will not be described here. Sufiice it to say that a PLO may oscillate parametrically in one phase'or a counter phase at a frequency f when energized by signals from a pump at a frequency 2f. Which phase the oscillations assume is determined by conditions existing in the tank circuit when the pump signals are applied. Oscillations may be steered into a selected phase by applying a small locking signal, at or near the desired phase, to the PLO prior to energization thereof. ff no locking signal is applied, however, the phase of oscillations is indeterminate. In the embodiment of FIG- URE 1, the summation of the input signals to the threshold organ is the locking signal which determines the phase of oscillations of the PLO. To prevent indeterminacy when X Y, a small signal having a phase representing binary "0 is applied as the threshold T.

FIGURE 2 illustrates one method of Weighting the information input signals When a PLO of the type illustrated and described in the article aforementioned is used as the threshold organ. The PLO cavity 40 may be a section of strip transmission line having a variable capacitance diode 41 mounted at one end, as described in the article aforementioned. The cavity is resonant at a frequency f. Input antennas are positioned adjacent the PLO cavity 40. Only three antennas 42, 44, d6 are illustrated in the drawing. Weighting of the input signals is accomplished by weighting the coupling constants of the antennas 42, 44, 46 to the cavity 40, as shown in FIGURE 2. Any phase shift of the input signals which results from Weighting the coupling may be compensated by suitable selection of input line length. An output antenna 48i's positioned adjacent the' cavity 40 to provide an output signal for transmission to the output terminal 14, or 22.' All of the antennas may be constructed of vstrip transmission line.

Parametric oscillations are sustained at a frequency f in the cavity i0 when pump signals of a frequency 2f are coupled to the cavity 40. The pump signals are transmitted to the cavity i0 over a section of strip transmission line 5t) from a source (not shown). A length of line 52 which is approximately an odd number of half wavelengths long at the pump frequency serves as a filter toprevent the oscillations of frequency f from beingfed back to the pump. The parametric oscillations may be damped periodically by interrupting the pump. Oscillations then resume in a phase determined by the locking signal when the pump signals are next applied. Other techniques for weighting the input signals to a strip transmission line'PLO include the use of directional couplers with properly Weighted coupling constants and the'use of a weighted power divider.

The complementingdevices 18, 26 of FIGURE l may be, for example, suitable lengths of transmission line when phase script signals are employed to represent the binary digits.' A transmission line an add number of half wavelengths long at the operating frequency serves to invert an alternating current signal. The third organ 30 may be another PLO of the type described to which is applied a threshold (Ta) signal in the form of a small radio frequency signal of frequency f and having a phase ondary winding 60a of a transformer 62a. The left end of the winding 60a is connected to the cathode of a voltage sensitive, Variable capacitance diode 64a. The negative terminal of a biasing source, illustrated as a battery 66a, is connected to the anode of the diode 64a. The right end of the secondary winding 60a is connected to the anode of a second variable capacitance diode 68a, the cathode thereof being connected to the positive terminal of a battery 70a. The negative terminal of the battery 70a and the positive terminal of the first battery 66a are connected to a point of reference potential, illustrated as circuit ground. The secondary winding 60a is center-tapped, and an inductor 72a is connected between the center tap and circuit one skilled in the art that only one resonant circuit is necessary for PLO operation. The particular configuration described above, however, has the advantage that components of the pump frequency developed across winding 6fm are cancelled out in the inductor 72a by action of two balanced, resonant circuits.

PLO2, on the right of the drawing, and PLO3, in the center of the drawing, are similar to PLOl and will not be described further. Like components of PLOs l, 2 and 3 are designated by like numerical reference characters followed by alphabetic characters a, b, c, respectively.

Phase script signals representing the binary digits x xn of a first binary quantity X are applied to a first plurality of input terminals of a weighted resistor input network 76a. Phase script signals representing the binary complements @o @n of the digits of a second binary quantity Y are applied to a second plurality of input terminals of the network 76a. The phase script signals are alternating current signals of one phase or a counter phase at the oscillating frequency gf of the PLOs.

Each of the input terminals is connected by a separate resistor to the top of the inductor 72a of the PLOl. The values of the resistors in the network 76a are chosen so that the signals applied to the PLOl are weighted inV accordance with their corresponding digit significance, as expressed, for example, by the coefficients in Equations 7 through 10. The phase script signal corresponding to x0, for example, is coupled to PLOl by a resistor having a value R; the signal corresponding to x, is coupled to PLOl by a resistor having a value R/ 2, and the signal corresponding to xn is coupled by a resistor having a value R/ 2n. Resistors for the other inputs x2 xn 1 are omitted for clarity. Consequently, the signals vcorresponding to x0, 'x1 xn reach PLOl with relative weights of 1, 2 2n, respectively. In like manner, signals corresponding to @0, @l En reach PLOl with relative weights of 1, 2 2, respectively.

Phase script signals representing the binary digits y0 yn of Y and binary complements 'n30 'in of the digits of X are applied to individual input terminals of a second weighted resistor input network 76b. This network V7 6b is similar to the first network 76a. The output of the weighted resistor network 76b is connected to the top of the inductor 72b in the PLO2.

The output of PLOl is applied to a first output terminal 14 over a line 16 which connects to the top of the inductor 72a. The output of PLOl is also coupled to the third PLO through a delay means 78a and a resistor 80a. The delay means 78a inverts or complements the output of PLOl to provide a signal corresponding to binary O when the input thereto is a binary 1, and vice-versa. The output of PLO2 is applied to an output terminal 22 over a line 24, and is also applied to PLO3 through a delay means 78b and a resistor 80h. The output of PLO3 is applied to an output terminal 32 over a line 34.

A PLO is essentially a two-terminal device having a common input-output terminal. Consequently, means must be provided to assure flow of information in one diground. It will be apparent to rection only. One method of obtaining transfer of information in a specified direction is to energize the PLOs of a system in timed sequence from a three phase pump, or from three separate pumps which provide an overlapping sequence of pump signals. A detailed description of three phase pumping applied to PLOs is given in an article by L. Onyshkevych et al. in the IRE Transactions on Electronic Computers, September 1959, at page 282.

In FIGURE 3, the three phase pump source is illustrated by a single block 84. The pump 84 provides the overlapping sequence of energizing signals illustrated in FIGURE 4. Energizing signals of phase l (P1) may be applied to the sources of the x and y input signals to the comparator. Energizing signals of phase 2 (P2) may be applied to PLOs 1 and 2 by way of transformer primary windings Sa and 86h, respectively, and energizing signals of phase 3 (P3) may be applied to PLO3 by way of transformer primary winding 86C.

Consider now the operation of the arrangement of FIG- URE 3. Pump signals of phase 1 and of a frequency 2f may be applied to the information PLO sources (not shown) at a time t1. the pump 84 at this time and, hence, do not oscillate. Digital information signals of frequency f are applied to the inputs of the weighted resister networks 76a, 76b from the information PLO sources. These signals are weighted according to digit significance by the resistors in the weighted resistor networks 76a, 76b, and the networks provide output signals of frequency f and of an amplitude representing the summation of the weighted signals.

If the binary quantity X is greater than Y, a binary l signal is supplied as a locking signal to PLOl Aby the resistor network 76a and a binary 0 signal is supplied as a locking signal to PLO2 by the other resistor network 7 6b. The locking signals supplied by these networks 76a, 76b are reversed if Y is greater than X. Phase `script signals have cancellation or veto power, as discussed hereinabove. Therefore, the information signals applied to the networks 76a, 76b cancel each other out if X is equal to Y. Ordinarily, therefore, no phase locking signal would be supplied to PLOs 1 and 2 when X Y, and the phase of oscillations of these PLOs would be indeterminate.

To prevent such indeterminancy, a small reference signal of frequency f and of a phase representing a binary 0 is supplied to each of the weighted resistor networks 76a, 76b. This reference signal may be viewed as a threshold signal. Accordingly, weighted resistor network 76a supplies a binary l locking signa to PLOl only when X is greater than Y, and supplies a binary 0 locking signal when X is equal to or less than Y. Weighted resistor netl work 76b supplies a binary 1 locking signal to PLO2 only when Y is greater than X.

The pump 84 supplies energizing signals at a frequency 2f to the PLOs l and 2 at a time t3. The outputs of the weighted resistor networks 76a, 76b are supplied as locking signals to PLOs 1 and 2, respectively, at this time, and oscillations build up in PLOs 1 and 2 at a frequency f in phase with the respective locking signals. The output of PLOl appears at the output terminal 14 and the output of PLO2 appears at the output terminal 22. A portion of the output of each of these PLOs is inverted and supplied to the third PLO. Also applied to PLO3 is a reference signal having a phase representing binary "0. The sum of these three signals determines the phase of oscillation of PLO3 when this PLO is energized by the pump 84 at a time t5. PLO3 provides a binary l output only when both information inputs thereto are binary 1, a condition existing only when X Y.

FIGURE 5 is a schematic diagram of a threshold organ 10 suitable for use in a baseband system wherein a binary l is represented by a pulse of one polarity, and

a binary O is represented either by the absence of a pulse or by a pulse of the opposite polarity. In the latter case, a binary "0 and a binary l signal of the same PLOs 1 and 2 are not energized by `90is. high at. this time. Vstate represented by the operating point c, the voltage weight cancel one another. No cancellation obtains in the former case. The circuit comprises the series combination of a tunnel diode 90, a resistor 92 and a voltage pulse source 94. The cathode of the tunnel diode 90 is connected to a point of reference potential, indicated as circuit ground. One terminal of the pulse source 94 is connected to ground; positive energizing pulses appear periodically at the other terminal' and across the resistor 92, diode 9d combination. Tunnel diodes and their characteristicsk arev described in detail in the article by H. S. Sommers, Jr. inA the Proceedings of the IRE, July 1959, at page 1201, and in other publications, and will not be describedherey except asis necessary to describe the operation of the circuit.

FIGURE 6 illustrates the operating characteristics of the FIGURE circuit. A curve 100 illustrates the voltampere characteristic ofy the tunnel diode 9). A load line 102, Whose slope is determined by the value of resistor 92, intersects thel characteristic curve ltltl at points a, b and c. The pointsl a and c intersect the curve Itl in regions of positive resistance and. are points of stable operation. The point b is` a point o-f intersection in the region of negative resistance and, for the indicated loading, the circuit cannot be maintained quiescently at this intersection point. The FIGURE 5 circuit, therefore, is bistable; that is, it has two stable operating states. When the circuit is in the state represented by operating point a, the voltage across. the diode 90 is relatively low, corresponding to binary 0. Conduction through the diode Whenthe circuit is in the stable across the diode 90 is relatively high, corresponding to binary 1, and diode conduction is low. In the absence of an information input pulse, the. diode 9i) assumes the low-voltage stable state whenL anenergizing pulsev 95 is applied. The diode 90 may be switched to. its high voltage state by increasing thecurrent through the diode 9.0-above a critical value corresponding to the current Ic indicated on the graph of FIGURE 6.

A plurality of-weighted resistors R1, R/yl R/ 2n of the type illustrated-in FIGURE 3 and described previously are connected between different input terminals and the anode of diode 9i); Signals representing the binary digits x0 xn and @o @n are applied at the appropriate input terminals. The weighted resistors are selected in value sothat anV input pulse atlany input terminalfsuppliesan amount of current or voltage to the circuit in correspondence with its digit signicance. For example, an input pulse corresponding to the digit x0 is applied to the anodeof the diode 90 through, a resistor R. An input pulse corresponding to the digit x1 is applied to the anode through a resistor R/2 and supplies twice as muchcurrent tothe tunnel diode 9h as the signal corresponding to thexo digit.

Thevalues of the resistor 92 and the energizing pulse 95- are selected soV that the tunnel diode 90 switches to the high voltage state andl provides an output pulse having a voltage Vb only if the sum of the inputs exceeds av certain value. The value of resistor 92 and the magnitude of the energizing pulse 95 thus determine the threshold of the tunnel diode circuit, and the values of these elementsrare chosen in accordance with Equation 12. If .the input pulses have cancellation power, as where a binary l is represented by a positivepulse, and a binary "0 isrepresented by al negative pulse, then theresistor 92may be selected to provide the load line 106 which intersects the: positive resistance region'otlow-voltage of thercurve 160 close to the peak of the curve. The tunnel diode 90, in this case, switches to the high voltage state when` the summation of the input signals has a small positive value. No switching occurs when the binary quantity X is equal to the quantity'Y.

FIGURE 7 is a schematic diagram of 'a circuit suitable fol-use asthecomplementing device 18, 26- of FIGURE not held to close tolerances.

10,-` 1. Operation of this circuit is similar to that of FIGURE 5. The FIGURE 7 circuit comprises the series combination of a resistor 110, a tunnel diode 90, a resistor 112 and' a pulse source 94, connected in that order. The values of the resistors 111i, 112 may be selected to provide the loadf line ltiof FIGURE 4.

A resistor 114 is connected between an input terminal 116 and the anode of the tunnel diode 90. In the absence of an input pulse 116, thev tunnel diode assumes the low voltage state corresponding to point d of FIG- URE 6 when the circuit is energized by a pulse from the pulse source 94.. The diode 90 conducts heavily at this time, andthe voltage at the output terminal 120 is then relatively high because of the voltage drop across the resistor 110. If, however, a positive input pulse 116, corresponding to a binary 1, is applied at the input terminal 116, the diode 90 switches to the high' voltage state of relatively low conduction, and the voltage at the Output terminal 120 is then low due to the reduced voltage drop across resistor 116i. A negative pulse (not shown), corresponding to a binary has the same eitect on the diode 9tlfas the absence of an input pulse, and does not switchthe tunnel diode from the low voltage state to the high voltage state. The FIGURE 7 circuit, therefore, may be used in a basebandy system wherein binary l is a positive pulse or level, and binary 0" is either the absence of a pulse or a negative pulse or level.

Threek phase pulse energizing techniques may be used in a baseband system employing tunnel diodes. The energizingpulses of different phase then overlap each other in the same manner as the RF bursts illustrated in FIGURE 4'. Of course, the pulse sources $4 may be replacedwith constant voltage sources if means are pro- Vvided for. periodically resetting the tunnel diodes to the low voltage state.

Insonie applications it may be necessary to limit the number of effective inputs in a threshold organ'if'reliable comparison results are to be obtained. Such a restriction may be due to limitations of the organ itself. In other cases, this restriction may become necessary when the phase and/or amplitude of the information signals are FIGURE 8 is a block diagram oi"V a comparator according to the invention wherein the number of eiective inputs to a threshold organ does not exceed seven. By efective inputs is meant the absolutesum of the weighted inputs.

Let it be desired to compare two four-digit, binary quantities X and Y, where X =x3x2x1x0 and Y=y3y2y1y0- In thev FIGURE 8 embodiment of the invention, this objective is achieved by (1) comparing xlxo with ylyo, (2) comparing; x4x3.with/ y4y3, and y(3) comparingV the results of (l). and"(2) with each other after properly weighting the results of( 1) andl (2).

Signals representing the binary digits x1, x0, @l and go arel applied as inputs to a first threshold organ 130, designated T.O. #1. These signals are weighted according to the ratio.v of their binary signicance by any of the means described previously, the particular means depending upon the type or" threshold organ employed. The signal input to theorgan representing the digit of lesser signiiicance is given'a weight of unity in this and in all other threshold' organs tovbe described. In like manner, signals representing the binary digits 51, 50, y1 and y0 are applied as inputs to a second threshold organ 132 and properly. weighted according to the ratio of their binary significance. The outputs of the rst and second threshold 'organs' 130 and 132 are designated x0 and y0', respec- 70 Y are applied to a third threshold organ 134 tively, for convenience.

Signalsrepresenting the binary digits x3, x2, Q3 andi/ and properly weighted as aforesaid, the digit of' lesser significance being given a weight of unity. Likewise, the signals representing the binary digits 53, 52, y3 and y2. are applied 11 as inputs to a fourth threshold organ 136. The outputs of the third and fourth threshold organs 134 and 136 `are designated x1 and y1', respectively.

Two additional threshold organs 138, 140 are provided for making a comparison between the derived quantities xlxo and yl'yo. The outputs x0 and x1' of the first and third threshold organs 130 and 134 are applied directly to the ifth threshold organ 138 and weighted as indicated by the numbers adjacent to the arrows on the input leads. These outputs are also complemented by devices 144, 146, applied to the sixth threshold gate 140 as signals representing 'JTO'. and E?, and Weighted as indicated.

The outputs y and y1 of the second and fourth threshold gates 132 and 136, respectively, are applied directly as inputs to the sixth threshold organ 140. These outputs also are complemented by devices 150, 152 and applied to the fifth threshold gate 138 as signals representing y? and The iifth threshold organ 138 thereby receives the sixth threshold organ 140 receives signals representing x1', xo, y1' and y0.

The output of the fifth threshold organ 138 is applied over a line 16 to an output terminal 14 and also is applied to the input of a complementing device 160. The output of the sixth threshold organ 140 is applied over a line 24 to a second output terminal 22, and also is applied to the input of a complementing device 162. The outputs of the complementing devices 160, 162 are applied to a seventh threshold organ 170.

Threshold (T) signals or voltages are applied to each of the iirst through sixth threshold organs 130 140. A threshold (T2) voltage or signal is applied to the seventh organ 170. The threshold may take any of the forms previously discussed, depending upon the type of device used as a threshold organ. In particular, if the threshold organs are PLOs, the thresholds (T) and (T2) may be small amplitude signals at the PLO oscillating frequency and having a phase representing a binary 0. The three phase pumping means are not illustrated in the generalized case of FIGURE 8. It will be apparent, however, that if PLOs are used as the threshold organs, the first, second, third and fourth organs are pumped during one clock period, the fifth and sixth organs are pumped during a second clock period, and the seventh organ is pumped during a third clock period. The information input sources then are also pumped during the third clock period. The clock periods may be as illustrated in FIGURE 4.

Operation of the FIGURE 8 arrangement may be understood best by considering a few examples. Let X=1ll1 and Y=101l, that is X is greater than Y. In accordance with Equataion `3, =0000 and =0l00. The quantity xlxo is equal to ylyo and, therefore, each of the outputs x0 and y0 of the iirst and second organs is a binary 0. Since x3x2 is greater than ygyz, the outsignals representing x1', x0', y1 and y0',

put x1 of the third organ 134 is a binary l and the output y0 of the fourth organ 136 is a binary 0. The iifth threshold organ 138 receives the binary l inputs x1' and The output of the iifth threshold organ 138 is, therefore, a binary l and the output of the sixth threshold organ 140 is a binary 0.

The binary l output of the lifth threshold organ 138 appears at the iirst output terminal 14 as an indication that X is greater than Y. This output is inverted and applied to the seventh threshold organ 170 as a binary 0. Because of the threshold'(Ta) applied to this organ 170, a signal or level representing binary 0 appears at the output terminal 32 in the presence of a binary 0 input. The binary 0 output of the sixth threshold organ 140 appears at the output terminal 22.

If X: Y, then each of the irst through the fourth organs Y1,30 136 provides an output representing a binary O because of the threshold (T). The ifth and sixth threshold organs 138, also provide binary 0 outputs for the same reason, and a binary 0 appears at each of the iirst and second output terminals 14 and 22. The binary 0 outputs of the fth and sixth threshold organs 138 and 140 are complemented by devices 160 and 162, respectively, to provide ir'st and second binary 1 input signals to the seventh threshold organ 170. The sum of these inputs exceeds the threshold (T2), and the seventh threshold organ then has a binary l output. This l output appearing at the output terminal 22 signals that X Y.

Consider now the case where Y is greater than X. Let Y=llll and X=lll0. The 17:0000 and =000L The output x0' of the irst threshold organ 130 is a binary 0 because xlxo is less than ylyo. The output y0 of the second organ 132 is a binary l for the same reason. The outputs x1' and y1 of the third and fourth organs 134, 136, respectively, are both binary 0 because x3x2=y3y2- The fifth threshold organ 138 lreceives a binary 0 signal representing x1 and a binary l signal representing y1', each signal having a relative weight of two. This organ 138 also receives two binary 0 signals representing x0 and y0', each signal having a relative weight of one. Consequently, the output of the fifth threshold gate 138 is a binary 0, and this output appears at the rst output terminal 14.

The sixth threshold organ 140 receives binary l signals representing 'if and y0', a binary 1 signal representing x1 and a binary 0 signal representing y1'. This organ 140, therefore, provides a binary l output signal. Such an output is to be expected since ylyo' (01) is greater than x1'x0 (00). This binary l output signal appearing at the second output terminal 22 signals that Y is greater than X. The output of the sixth threshold organ 140 is complemented by the device 162 and applied to the seventh threshold organ 170 as a binary 0 signal. Because of the threshold (Ta) of this organ, and the binary 0 input, a binary 0 output is provided by this organ 170 and appears at the output terminal 32.

It will be apparent to those skilled in the art that any of the threshold devices illustrated in FIGURES 2, 4, and 5 are suitable for use as the threshold organs in the FIGURE 8 arrangement. It is t0 be understood, however, that the invention is not limited to these devices only. It will also be apparent that binary quantities of more than four digits may be compared according to the teachings of FIGURE 8 and the accompanying description by a suitable pyramiding of threshold organs.

What is claimed is:

l. A comparator for comparing first and second multidigit binary quantities comprising, in combination: first and second threshold organs; means for applying to said lirst and second organs weighted signals representing the binary digits of said first and second quantities, respectively; means for applying to said iirst and second organs weighted signals representing the bit by bit binary cornplements of the digits of said second and first quantities, respectively; and signal responsive means connected to the outputs of said Afirst and second organs.

`2. A comparator for comparing a first binary quantity and a second binary quantity comprising, in combination: a iirst threshold lorgan and va second threshold organ; means for applying to said first organ signals representing the binary digits of said first quantity and the bit by bit binary complements of the binary digits of said second quantity; means for yapplying to said second organ signals representing the binary digits lof said second quantity and the bit by bit binary `complement-s of saidirst quanti-ty; means for Weighting said signals according to their digit significance; and output mean-s connected to receive the outputs of the `first and second organs.

3. A compara-tor for comparing first and second multidigit binary quantities comprising, in combination: first and second threshold organs; means for applying to said first and second organs signals weighted according to digit significance in said quantities and representing the binary digits of said first and second quantities, respectively; means for applying to said first and second organs signals weighted according to digit significance in said quantities and representing the bit by bit binary complements of the binary digits of said second and 'first quantities, respectively; first and second output terminals connected to the outputs of said first and second threshold organs, respectively; and signal responsive means connected t receive the outputs of said first and second organs.

4. A comparator `for comparing a first multidigit binary quantity and a second multidigit binary quantity, comprising: a first organ and a second organ, means for applying to said first organ weighted signals representing the binary digits of said first quantity and weighted signals representing the binary complements of the digits of said second quantity, means for applying to said second organ weighted signals representing the binary digits of said second quantity and weighted signals representing the binary complements of the digits of said 4first quantity, each of said `signals being weighted in accordance with the significance in the quantity `of the corresponding digit, said first organ having a threshold such that said first organ provides a first output only 'when said first quantity has the larger binary value and provides a second 'output at all other times, said secon-d organ having a threshold such that said second organ provides said first output only when said second quantity has the larger value and provides said second output at all other times, and signal responsive means connected to receive the outputs of the first and second organs.

5. The comparator as claimed in claim 4 wherein each of said first organ and said second organ is `a tunnel diode bistable circuit.

6. The comparator as claimed in claim 4 wherein said signal responsive means provides said first .output when said rst organ land said second organ are both providing said second output.

7. AIn an information handling system wherein the binary digits one and zero are represented by alternating current signals of one phase and a counter phase, respectively, at the same frequency, a comparator for comparing first and second m-uitidigit binary quantities comprising, in combination: first and second phase locked oscillators each having two stable phases of oscillation at said frequency, said two phases corresponding to binary one and zero; means for applying to said first and second yoscillators signals weighted according to digit significance and representing, respectively, the digits 0f Said first and second quantities; means for applying to said first and second oscillators signals weighted according to digit significance and representing the bit by bit binary complements of the digits of said second and first quantities, respectively; and signal responsive means connected to receive the outputs of said first and second oscillators.

8. The comparator a-s claimed in claim 7, wherein said signal responsive means is a third phase locked oscillator.

v9. IIn yan information handling system wherein the binary digits one and zero are represented by alternating current signals of one phase and a counter phase, respectively, at the same frequency, a comparator for comparing first and second multidigit binary quantities comprising, in combination: first and second phase locked oscillators each having two stable phases of oscillation at said frequency, said two phases corresponding to binary one and Zero; means for applying to said first and second oscillators signals weighted according to digit significance and representing the digits of said first and second quantities, respectively; means for applying to said first and second oscillators signals weighted according to digit significance and representing the bit by bit binary complements of the digits of said second and first quantities, respectively; and means for applying a reference threshold signal of said frequency to said first and second oscillators.

l0. The comparator as claimed in claim 9 wherein said reference threshold signal has a phase corresponding to binary zero 1l. The comparator as claimed in claim 10, wherein said output means includes means for inverting the outputs .of said' Ifirst and second oscillators, and a third phase looked oscillator connected to receive said inverted outputs and said reference signal.

12. A comparator for comparing a first multidi-git binary quantity and a second multidigit binary quantity comprising: a first threshold organ and a second threshold organ; means for applying to said first organ signals representing the digits of said first quantity and the binary complements of the digits of said second quantity, Said signals being weighted according to corresponding digit significance; means for applying to said second organ signals representing the digits of said second quantity and the binary complements of the digits of said first quantity, said signals being weighted according to digit significance; and a ythird threshold organ connected to receive the outputs of said first organ and said second organ.

13. The comparator as claimed in :claim 12 including a first output means connected to the output of said rst threshold organ, a -second output means connected to the output of said second threshold organ, and a third output means connected to the output of said third threshold organ.

14. Apparatus for comparing a first binary quantity X=xn xlxo and a second binary quantity Y=yn ylyo comprising: first means for weighting according to digit significance signals representing the binary digits xn xlxo of X and signals representing the binary complements 31 yiyo Of the digits of Y; a first threshold organ connected at its 'input to said first weighting means for providing a first output when the sum of' the weighted signals provided by said first weighting means is greater than and said second output at all other times; and signal responsive means connected to receive the outputs of the first and second organs.

15. The apparatus as claimed in claim 14, wherein said signal responsive means provides said yfirst output when said first organ and said second organ both provide said second output.

References Cited in the file of this patent UNITED STATES PATENTS Smoliar May 5, 1959 Davey Oct. 4, 1960 ent requiring correction and that the sa ESTON G. JOHNSON Attesting Officer UNITED STATES PATENT OEEICE 'l CERTIFICATE 0F CORRECTION Patent No. 3,124,677

March lO', '1964 Henry S. Miiller 1 It is `hereby certified that error appears in the above numbered patd Letters Patent Should read as corrected below.

Column 2, line 40, for "is noted" read -e is toV be nOted line 43, for "coefficient" read coefficients column 3, line 9, vfor "the bit One's" reeel the bit by bit One's column 4, line lO, for "XD" read YD line 5l, after "binary" insert digits line 60, for "thereinafter" read hereinafter column 14, line 40, for

ynnuecylyo" read m ynu.ly0

Signed and sealed this'28th day of July 1964.

(SEAL) Attest:

EDWARD J. BRENNER Commissioner of Patents UNITED STATES PATENT OFFICE A CERTIFICATE 0F CORRECTION Patent No. 3, 124,677 March IO, '1964 Henry So Miiller It is hereby certified that error appears in the above numbered patent requiring correction and that the said Letters Patent should read as corrected below.

Column 2, line 40, for "is noted" read is tov be noted line 43, for "coefficient" read coefficients column 3, line 9, for "the bit one's" read the bit by bit one's column 4, line lO, for "XD" read YD line 5l, after "binary" insert digits line 60, for "thereinafter" read hereinafter column I4, line 40, for

"ym ,.ylyo" read -M yno .$71570 Signed and sealed this'28th day of July 1964.

(SEAL) Attest:

ESTON G. JOHNSON EDWARD J. BRENNER Attestng Officer Commissioner of Patents 

1. A COMPARATOR FOR COMPARING FIRST AND SECOND MULTIDIGIT BINARY QUANTITIES COMPRISING, IN COMBINATION: FIRST AND SECOND THRESHOLD ORGANS; MEANS FOR APPLYING TO SAID FIRST AND SECOND ORGANS WEIGHTED SIGNALS REPRESENTING THE BINARY DIGITS OF SAID FIRST AND SECOND QUANTITIES, RESPECTIVELY; MEANS FOR APPLYING TO SAID FIRST AND SECOND ORGANS WEIGHTED SIGNALS REPRESENTING THE BIT BY BIT BINARY COMPLEMENTS OF THE DIGITS OF SAID SECOND AND FIRST QUANTITIES, RESPECTIVELY; AND SIGNAL RESPONSIVE MEANS CONNECTED TO THE OUTPUTS OF SAID FIRST AND SECOND ORGANS. 